The parallel form of the input sequence is decoded by means of a logical decoding circuit . 此并行形式序列通過邏輯解碼電路輸入。
An application of logic devices able to program to the decoding circuit 可編程邏輯器件在譯碼電路中的應(yīng)用
Colour decoding circuit 彩色解碼電路
The results of p & r demonstrate that this design constructs a rs encoding / decoding circuit with a 3 . 2k internal fifo cache embedded , at the scale of 46k gates . its encoding and decoding speed are 66mhz and 47mhz respectively 布局布線后結(jié)果表明本文所設(shè)計的rs編碼器的速度可達到66mhz ;解碼速度可達到47mhz ,電路規(guī)模為4 . 6萬門,包含有3 . 2k的內(nèi)部緩存fifo的rs編/解碼電路。
The hardware system includes power supply circuit , clock reset circuit , jtag model building circuit , decoding circuit , memory interface circuit , man - machine interface circuit and numeric control constant - current source interface circuit 硬件系統(tǒng)主要包括電源電路、時鐘復(fù)位電路、 jtag仿真接口電路,譯碼電路、存儲器接口電路、人機接口電路、 adc轉(zhuǎn)換電路和數(shù)控恒流源接口等。
Chapter two addresses in details systematic design and related modules of stand - alone door - lock system . the modules include mcu , recognition module , power , lcd , guide voice , i / o decoding circuit , rtc , unlock circuit , power save and anti - interference design 第二部分著重介紹了指紋門禁單機系統(tǒng)的系統(tǒng)總體設(shè)計以及系統(tǒng)中涉及到的各模塊的基礎(chǔ)知識、設(shè)計思路和具體實現(xiàn)。
In this paper we discuss mca circuit , the sequential logic for mca data collection , for the setting of the uld , lld and the gain of pga , as well as the combinational logic for decoding circuits of the computer interface , based on cpld 本文詳細論述了利用cpld實現(xiàn)的脈沖幅度多道電路及其數(shù)據(jù)采集的時序控制邏輯、閾值設(shè)定和程控放大倍數(shù)設(shè)定的時序控制邏四川大學碩士學位論文輯、以及與計算機接口的譯碼電路等組合控制邏輯。
The application of hardware decoding circuit is widely , because it not only can be used on computer , but also can be used on consumer equipment like digital - tv and dvd - player . the avs and h . 264 standards and the architecture of digital video decoder chip are investigated in the thesis , and a high - definition multi - mode decoder soc chip is proposed . the chip can support avs level 4 . 0 / 6 . 0 and h . 264 main profile level 4 . 0 本文在研究了avs和h . 264視頻編碼標準和數(shù)字視頻解碼芯片系統(tǒng)結(jié)構(gòu)的基礎(chǔ)上,設(shè)計了同時支持avs和h . 264的高清解碼soc芯片,能夠?qū)vslevel4 . 0 / 6 . 0和h . 264mainprofilelevel4 . 0的高清晰度視頻碼流實時解碼。
It emphatically describes address decoding circuit and controling circuit of fpga in hardware , and describes dma transmission mode and disposing of the interrupt in driver , and describes how to get data from wav file , and how to organize data before transmition , and how to chose appropriate quantity of data transmition every time in application 著重闡述了硬件設(shè)計中fpga內(nèi)部重要的譯碼及控制電路設(shè)計,驅(qū)動程序中dma ( directmemoryaccess )的傳輸及中斷處理,應(yīng)用程序中對于兩個聲音文件數(shù)據(jù)的正確獲取、組合及分割等問題。
There are several aspects of work that was done in this thesis mainly . firstly , the theory of the under - water long - range remote control system was analyzed and the remote control instruction code was designed . secondly , decoding circuit of the under - water long - range remote control system was designed with fpga , including vhdl coding , simulation , synthesis , place & route , etc . besides , power consumption to fpga that is designed is estimated in this thesis . lastly , we designed and made one pcb to verify and test fpga decoding chip that is designed , and debugged and tested it finally 首先,深入研究和分析了在頻域?qū)崿F(xiàn)水下遠程遙控解碼的原理并進行了遙控指令編碼設(shè)計;其次,用altera公司的cyclone系列fpga芯片完成了水下遠程遙控fpga解碼芯片的設(shè)計工作,包括硬件描述語言( vhdl )編碼、電路前后仿真、綜合和布局布線工作,并對設(shè)計的fpga解碼芯片進行了初步的功耗估算;最后設(shè)計制作了一塊fpga解碼芯片電路驗證測試板,并完成了電路調(diào)試和測試。